Warpage control of silicon interposer for 2.5D package application

In order to achieve high speed transmission and large volume data processing, large size silicon-interposer has been required. Warpage caused by the CTE mismatch between a large silicon-interposer and an organic substrate is the most significant problem. In this study, we investigated several warpage control techniques for 2.5D package assembly process. First was assembly process sequence. One is called “chip first process” that is, chips are mounted on Si-interposer at first. The other is called “chip last process” that is, silicon-interposer is mounted on organic substrate at first and chips are mounted on at last. The chip first process successfully processed using conventional mass reflow. By using the chip first process, apparent CTE of a large silicon-interposer become close to that of an organic substrate. Second was the warpage control using underfill resin. We focused on the selection of underfill materials for 0 level assembly. And third was the warpage control technique with Sn-57Bi solder using conventional reflow process. We observed warpage change during simulated reflow process using three-dimensional digital image correlation system (3D-DIC). Sn-57Bi solder joining has been noted as a low temperature bonding methods. It is possible to lower peak temperature 45-90 degree C during reflow compared with using Sn3.0wt%Ag0.5wt%Cu (SAC305). By using Sn-57Bi solder, the warpage after reflow was reduced to 75% of that using SAC305. The full assembly was successfully processed using conventional assembly equipment and processes. The full assembly packages were evaluated by some reliability tests. All samples passed each reliability test.