Integration challenges of TSV backside via reveal process

Through-Silicon Vias [TSV] offer a method to improved electrical signal speeds by reducing interconnect length. Via Reveal - a wafer back side process steps - is key to the successful implementation of TSV. After via formation, finished CMOS wafers or interposers are temporarily bonded with glass carriers. The TSV are will be `Revealed´ using include Si back-grind and plasma etch steps, and then passivated with PECVD, finally, use CMP to open Cu pillar. Via reveal processes must maintain acceptably low Total Thickness Variation (TTV) to allow subsequent bonding/stacking steps. Process temperature must lower than carrier bonding adhesives - a particular challenge for dielectric deposition. Data on Silicon etching will show that etch rate > 3.8μm/min, with Cu pillar TTV<;2μm and selectivity to liner oxide around ~100 can be achieved on bonded wafers. A silicon etched profile control method by chemical gases flow and pressure change will be presented. For backside metal line process that needs developed low wet rate dielectric film, result showed wet etch rates in the chemical solution was improved from >116nm/min to <;22nm/min, these film also show excellent conformability on backside TSV that step coverage >80%. It also have good uniformity and pass electrical test. Dielectric film/Cu CMP process is applied for protrude the backside TSV coplanarly, the shape of backside TSV will be well control by CMP remove rate and end-point detect.