Author :
Eslampour, Hamid ; Joshi, Madhura ; KyungOe Kim ; Sun Wei ; JaeHan Chung ; Taewoo Lee ; HangChul Choi ; Emigh, Roger
Author_Institution :
STATSChipPAC, Fremont, CA, USA
Abstract :
The adoption of Tablet devices within the mobile communication space and its penetration into the market segment once held by laptops has resulted in explosive growth rate of these devices, and as a result has created new requirements for the packaging of Application Processors (AP) used in these devices. These requirements and trends are similar to those seen within the Smartphone space and include die size increase, and thinner profile within the same package footprint. The increased performance power of APs enabled through higher frequency computing, which has led to this die size increase, has also resulted in increased thermal power, and also more stringent electrical performance requirements imposed on power delivery system. To address the power delivery requirements, chip capacitors are used to improve transient response of the processors at these high frequencies while Heat-Spreader (HS) solution is implemented to address the thermal power requirements. The integration of chip capacitors, larger die size, and HS in thinner package profiles, have led to evolution of new package technologies and configurations, which are outlined in this paper. One such configuration is the thinned-down discrete Flip Chip Ball Grid Array (FCBGA) with HS. The enablement of this thinner package is done through development and qualification of thinner core and substrate materials, in combination with thinner Silicon die, thinner HS, and lower Ball Grid Array (BGA) stand-off height. The resulting thinned-down package structure poses challenges in meeting package warpage and coplanarity specs, which can only be solved by optimization of process and Bill Of Material (BOM). Current packages in development, mainly in 28nm FAB node, are designed and being qualified to meet max package height of 1.4mm, with integrated HS configuration while the next generation package technology is pushing the max height requirement to below 1.4 mm with the same integrated HS configuration. To achieve - his lower height, package configuration is changed to Exposed Die Molded FCBGA with integrated HS where the utilization of the mold cap improves the package warpage due to mold shrinkage factor, while also allowing for a smaller package body size. Alternatively, the same package could be offered without the HS, achieving yet thinner height, while the exposed die backside leads to improved thermal performance through natural convection. This paper outlines the above various package configurations, their features, relative performance, and their assembly process. Furthermore, the next generation technologies to enable yet the thinner profile packages, as required by market trends, are outlined with their key challenges.
Keywords :
ball grid arrays; bills of materials; flip-chip devices; microassembling; microprocessor chips; mobile communication; smart phones; thermal management (packaging); transient response; BGAstand-off height; BOM; FAB node; HS solution; application processors; assembly process; bill of material; chip capacitors; coplanarity specs; die backside; die size increase; electrical performance requirements; exposed die molded FCBGA; frequency computing; heat-spreader solution; integrated HS configuration; market segment; mobile communication space; mold shrinkage factor; natural convection; next generation package technology; next generation technology; package configurations; package footprint; package warpage; power delivery requirements; power delivery system; profile flip chip packages; profile packages; relative performance; silicon die; smartphone space; substrate materials; tablet devices; tablet processor; thermal performance; thermal power requirements; thinned-down discrete flip chip ball grid array; thinned-down package structure; thinner core; thinner package profiles; transient response; Assembly; Compounds; Market research; Reliability; Strips; Substrates;