Via-middle through-silicon via with integrated airgap to zero TSV-induced stress impact on device performance

In the study, we report for the first time a novel concept for the mitigation of the TSV-induced stress on the CMOS device performance. This solution consists in selectively integrating an airgap at the time of via-middle TSV processing. In addition to the expected benefits in term of stress management, this new approach is also cost effective, as the TSV processing steps, such as deep silicon etching, Cu electroplating, and chemical mechanical polishing remain unchanged. The processing development and the results of the morphological and electrical characterization are given in details in this study. All in all, TSV with integrated airgap is a very versatile building block for TSV integration in presence of stress sensitive next generation of CMOS devices.