DocumentCode :
628578
Title :
Hermetic wafer level packaging of MEMS components using through silicon via and wafer to wafer bonding technologies
Author :
Zoschke, K. ; Manier, C.-A. ; Wilke, M. ; Jurgensen, Nils ; Oppermann, H. ; Ruffieux, David ; Dekker, James ; Heikkinen, H. ; Dalla Piazza, S. ; Allegato, G. ; Lang, K.-D.
Author_Institution :
Fraunhofer IZM, Berlin, Germany
fYear :
2013
fDate :
28-31 May 2013
Firstpage :
1500
Lastpage :
1507
Abstract :
This paper presents the fabrication steps of a MEMS package based on silicon interposer wafers with copper filled TSVs and bonded cap wafers for hermetic sealing of resonator components. All processes were performed at 200 mm wafer level. For interposer fabrication a standard process flow including silicon blind hole etching, isolation, copper filling, wafer front side redistribution, support wafer bonding, wafer thinning, and TSV backside reveal was applied. As interposer backside metallization, appropriate I/O terminals and seal ring structures were deposited by semi-additive Au and Au+Sn electro plating. Following, getter material was deposited onto the interposer wafers which were 90 μm thick and still mounted onto carrier wafers. Subsequently, the I/O terminal pads of the interposer were stud bumped and finally more than 5000 quartz resonator components were assembled onto each interposer wafer by Au-Au direct metal bonding. The cap wafer was equipped with 200 μm deep dry etched cavities and electro plated Au seal rings around them. Finally, both cap and interposer wafers were bonded together using a wafer to wafer bonder and an adapted AuSn soldering process scheme. In a last step, the carrier wafer was removed from the former front side of the interposer wafer and wafer level testing was performed. From a total of 4824 tested devices we found that more than 75 % were sealed properly under vacuum. The getter appears to be effective leading to ~0.1 mbar equivalent air pressure and cavities without getter appear to reach residual air pressure between 1-2 mbar. The used fabrication processes and final results will be discussed detailed in this manuscript.
Keywords :
electroplating; elemental semiconductors; gold compounds; micromechanical devices; silicon; three-dimensional integrated circuits; wafer level packaging; AuSn; I/O terminal pads; I/O terminals; MEMS package; Si; TSV; blind hole etching; bonded cap wafers; copper filling; depth 200 mum; direct metal bonding; electroplating; hermetic sealing; hermetic wafer level packaging; interposer backside metallization; interposer fabrication; isolation; quartz resonator components; seal ring structures; silicon interposer wafers; size 200 mm; size 90 mum; soldering process scheme; support wafer bonding; through silicon via; wafer front side redistribution; wafer thinning; wafer to wafer bonding technologies; Copper; Fabrication; Gettering; Gold; Micromechanical devices; Seals; Silicon;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd
Conference_Location :
Las Vegas, NV
ISSN :
0569-5503
Print_ISBN :
978-1-4799-0233-0
Type :
conf
DOI :
10.1109/ECTC.2013.6575770
Filename :
6575770
Link To Document :
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