Practical investigations of fiber weave effects on high-speed interfaces

In this paper, we investigate and quantify fiber weave effects on state-of-the-art high speed memory and SerDes (serialization-deserialization) interfaces. It has been discussed that the fiber weave effects in embedded systems do not pose a risk because typical trace lengths are short. We demonstrate that even in such cases, fiber weave effects can consume valuable timing margin in high speed channels. For this analysis, we consider the micro-scale composition of PCB laminates in order to create realistic two- and three-dimensional models incorporating fiber weave effects. We then assess the fiber weave effect impact on the quality and integrity of high speed signals on typical memory and SerDes channels on a PCB design targeting a generic mobile platform. Specifically, we investigate the potential risk that fiber weave effects can present in high speed SerDes channels. Two primary effects are investigated: time skew on DRAM systems and intra- and inter-pair skew in SerDes channels. Both effects are the result of local variations of the dielectric characteristics of the PCB substrate with position. In addition, we briefly discuss the underlying physical mechanisms originating these problems and review the pros and cons of mitigating techniques.