Design, fabrication and assembly of a novel electrical and microfluidic I/Os for 3-D chip stack and silicon interposer

A novel chip I/O technology, which enables high-bandwidth signaling, embedded microfluidic cooling and power delivery for high-performance 2.5D (silicon interposer) and 3D integrated circuits is presented. It features annular-shaped fluidic microbumps with 150 μm inner diameter and 210 μm outer diameter and fine-pitch electrical microbumps with 25 μm diameter and 50 μm pitch. Silicon dice with the novel electrical and fluidic I/O interconnections and die-level embedded microfluidic cooling were successfully fabricated and assembled. Following assembly, the measured resistance of a single electrical microbump is 13.50 MΩ ± 1.82 MΩ. Fluidic testing was conducted by pumping DI water into the bonded dice at a flow rate of up to 50 mL. No leakage or pressure drop change occurred during testing, and thus, demonstrating the feasibility of the novel fluidic I/O interconnections. In addition, the impact of the number of power delivery microbumps and die thickness (as a result of embedded microfluidic cooling) on power supply noise is analyzed using a compact physical model.