Homogenization of TSV interposer and quick assessment of its thermomechanical influence on 3D packages

Thin and filled with the through-silicon cupper via (TSV) array, silicon interposers are key to vertical integration of chips for denser packaging. TSVs reduce the trace length by directing electrons vertically through stacks of chips, so better electrical performance with less power consumption is made feasible. The via-enriched silicon interposer, albeit thin, can also serve as a stress buffer to mechanically modulate stresses among the components. In this regard, the effectiveness of being a stress buffer is poised to a design optimization problem. Due to the great discrepancy of the thermal expansion capacity between the silicon (less thermally deformable) and copper (more thermally deformable), the thermo-mechanical stress within the TSV interposer and its influence on the package is a concern. Although the thermomechanical behavior of the TSV interposers is acquainted, the understanding is often gained through detailed, predictive modeling of a specific TSV design and then deduced to other designs of similar structural configurations. The proposed work is aimed at developing a quick assessment technique as a preliminary tool to evaluate the TSV design before conducting rigorous modeling and experiments. This technique is focused on two aspects, as a preliminary evaluation of the thermo-mechanical response of an individual TSV structure, and as a platform for evaluating the interaction of the TSV interposer with other contingent layers in the package. This paper will first present a homogenized TSV model based on dilute homogenization, and then provide a theoretical description of the interfacial thermo-mechanical stress between the homogenized TSV interposer and its contingent layers. The results show that the interfacial shearing stress and peeling stress are increased as the volume fraction of the copper vias increases.