Stress analysis in 3D IC having Thermal Through Silicon Vias (TTSV)

Author

Patel, Shabaz Basheer ; Ghosh, T. ; Dutta, Arin ; Singh, Sushil

Author_Institution

Electr. Eng. Dept., IIT-Hyderabad, Hyderabad, India

fYear

2013

fDate

28-31 May 2013

Firstpage

2337

Lastpage

2341

Abstract

TTSV is proposed for the removal of heat from between the IC layers as these TTSVs carries heat down to the sink. However, it may generate stress in Silicon. In the present paper, thermal-stress simulation of stack consists of three IC layers bonded face up is performed using finite element modeling tools. We also analyzed the stress generated in 3D IC containing TTSV. Further we proposed a method for lower stress around the TTSV. The method proposed decreases the Von Misses Stress by a value of 40Mpa on average considering all the IC layers. Thus by achieving this, functionality of the chip becomes more reliable.

Keywords

finite element analysis; heat sinks; integrated circuit bonding; integrated circuit reliability; stress analysis; thermal stresses; three-dimensional integrated circuits; yield stress; 3D IC; IC layer bonding face up; TTSV; Von Misses stress; finite element modeling tool; heat removal; heat sink; reliability; stacking; thermal through silicon vias; thermal-stress simulation analysis; Heating; Integrated circuits; Mathematical model; Silicon; Stress; Substrates; 3D IC; CNT (Carbon Nano Tube); CVD Diamond; TTSV;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Conference_Location

Las Vegas, NV

ISSN

0569-5503

Print_ISBN

978-1-4799-0233-0

Type

conf

DOI

10.1109/ECTC.2013.6575910

Filename

6575910