An experimental verified model for Cu electrodeposition simulation for the filling of high aspect ratio through silicon vias

Author

Heng Wu ; Zhen-an Tang ; Zhu Wang ; Wan Cheng ; Chongsheng Song ; Daquan Yu ; Lixi Wan

Author_Institution

Dalian Univ. of Technol., Dalian, China

fYear

2013

fDate

28-31 May 2013

Firstpage

2366

Lastpage

2370

Abstract

The super-filling of high aspect ratio through silicon vias (TSVs) is a technical challenge for 3D integration. For optimizing the super-filling, the numerical simulation models of copper electro-deposition with suppressor and accelerator are founded. The arbitrary Lagrange-Eulerian (ALE) method for solving moving boundaries in finite element model (FEM) is used to simulate the electrochemical process. The simulation can predict the behavior of Cu electro-deposition, and the influence of concentration of suppressor was investigated. The simulations of the bottom-up copper electro-deposition are verified by experiment results. TSVs with diameter of 20 μm and depth of 200 μm without voids or seams have been achieved in the experiments.

Keywords

copper; electrochemical analysis; electrodeposition; elemental semiconductors; finite element analysis; integrated circuit testing; silicon; three-dimensional integrated circuits; 3D integration; ALE method; Cu; FEM; Si; TSV; accelerator; arbitrary Lagrange-Eulerian method; bottom-up copper electrodeposition; electrochemical process; electrodeposition simulation; finite element model; high aspect ratio through silicon vias; moving boundaries; numerical simulation model; super-filling; suppressor; Additives; Cathodes; Copper; Filling; Numerical models; Surface treatment; Through-silicon vias;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Components and Technology Conference (ECTC), 2013 IEEE 63rd

Conference_Location

Las Vegas, NV

ISSN

0569-5503

Print_ISBN

978-1-4799-0233-0

Type

conf

DOI

10.1109/ECTC.2013.6575915

Filename

6575915