Title :
BIST of interconnection lines in the pixel matrix of CMOS imagers
Author :
Fei, Richun ; Moreau, Julien ; Mir, Salvador
Author_Institution :
STMicroelectron., Grenoble, France
Abstract :
Interconnection lines in the sensors of CMOS imagers are used for pixel bias, addressing and readout. Catastrophic faults in these lines can cause parts of the pixel matrix to operate incorrectly and produce image defects like residual stripes and bands in images. These kinds of image defects are often difficult to remove by the image processing correction algorithm, and they are clearly visible as a sort of noise pattern. Among the defects in the pixel array, these catastrophic faults have most important influence on yield. In addition, partially degraded metal lines cannot be detected on todays´ standard industrial testers for image sensors. These defects can evolve into catastrophic faults and they are the main cause of customer returns for many products. This paper proposes two built-in self-test (BIST) solutions to catch these defects in the pixel array, taking into account the industrial test constraints, namely increase of fault coverage, decrease of test time and test cost minimization.
Keywords :
CMOS image sensors; built-in self test; cost reduction; fault diagnosis; integrated circuit interconnections; integrated circuit testing; BIST; CMOS image sensor; built-in self-test; catastrophic fault coverage; image band; image defect production; image processing correction algorithm; industrial tester; interconnection line; partially degraded metal line; pixel matrix array; residual stripe; test cost minimization; Circuit faults; Delays; Electrical resistance measurement; Photodiodes; System-on-chip; Table lookup; Voltage measurement; CMOS image sensors; HFPN; industrial test;
Conference_Titel :
Advances in Sensors and Interfaces (IWASI), 2013 5th IEEE International Workshop on
Conference_Location :
Bari
Print_ISBN :
978-1-4799-0039-8
DOI :
10.1109/IWASI.2013.6576068