Title :
An extra low-power 1Tbit/s bandwidth PLL/DLL-less eDRAM PHY using 0.3V low-swing IO for 2.5D CoWoS application
Author :
Mu-Shan Lin ; Chien-Chun Tsai ; Chih-Hsien Chang ; Wen-Hung Huang ; Ying-Yu Hsu ; Shu-Chun Yang ; Chin-Ming Fu ; Mao-Hsuan Chou ; Tien-Chien Huang ; Ching-Fang Chen ; Tze-Chiang Huang ; Adham, Saman ; Min-Jer Wang ; Shen, William Wu ; Mehta, A.
Author_Institution :
HSCD/DTP, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
A 1Tbit/s bandwidth PHY is demonstrated through 2.5D CoWoS platform. Two chips: SOC and eDRAM have been fabricated in TSMC 40nm CMOS technology and stacked on another silicon interposer chip in 65nm technology. Total 1024 DQ bus operating in 1.1Gbit/s with Vmin=0.3V are proven in experimental results. A novel timing compensation mechanism is presented to achieve a low-power and small area eDRAM PHY that excludes PLL/DLL but retains good timing margin. Another data sampling alignment training approach is reserved to enhance timing robustness. A compact low-swing IO also achieves great power efficiency of 0.105mW/Gbps.
Keywords :
CMOS integrated circuits; DRAM chips; compensation; elemental semiconductors; low-power electronics; silicon; system-in-package; system-on-chip; 2.5D CoWoS platform; DQ bus; PLL-DLL; SOC; Si; TSMC CMOS technology; bit rate 1.1 Gbit/s; compact low-swing IO; data sampling alignment training approach; silicon interposer chip; size 40 nm; size 65 nm; small area eDRAM PHY; timing compensation mechanism; voltage 0.3 V; Clocks; Phase locked loops; Silicon; Stacking; System-on-chip; Timing; Training;
Conference_Titel :
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5226-0
