DocumentCode
629112
Title
1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
Author
Jing Li ; Montoye, R. ; Ishii, M. ; Stawiasz, Kevin ; Nishida, Tsutomu ; Maloney, Kim ; Ditlow, Gary ; Lewis, Simon John Geoffrey ; Maffitt, T. ; Jordan, Ramiro ; Chang, Ly-Yu ; Peilin Song
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2013
fDate
11-13 June 2013
Abstract
This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10× smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin~750mV) and a match delay of 1.9 ns under nominal operating conditions.
Keywords
CMOS memory circuits; content-addressable storage; phase change memories; 2-transistor/2-resistive-storage; 2T-2R cell; IBM CMOS technology; clocked self-referenced sensing; low voltage search operation; mushroom phase change memory process; nonvolatile TCAM; reliable search operation; size 90 mum; storage capacity 1 Mbit; ternary content addressable memory; two bit encoding; Arrays; Clocks; Encoding; Microprocessors; Phase change materials; Sensors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location
Kyoto
ISSN
0743-1562
Print_ISBN
978-1-4673-5226-0
Type
conf
Filename
6576610
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