A 20nm 0.6V 2.1µW/MHz 128kb SRAM with no half select issue by interleave wordline and hierarchical bitline scheme

For 20nm SoC products, we propose an SRAM macro with low dynamic and leakage power. This is achieved by adopting an interleave word-line and hierarchical bit-line scheme, in which minimum portions of circuits are activated when SRAM is accessed. Measured data confirms that the proposed 128kb SRAM realizes 600 mV operation, 2.1 μW/MHz active power and 82 % leakage power reduction.