DocumentCode :
629128
Title :
Ultralow-voltage operation of Silicon-on-Thin-BOX (SOTB) 2Mbit SRAM down to 0.37 V utilizing adaptive back bias
Author :
Yamamoto, Yusaku ; Makiyama, Hideki ; Shinohara, Hirofumi ; Iwamatsu, Takanori ; Oda, Hidekazu ; Kamohara, Shiro ; Sugii, Nobuyuki ; Yamaguchi, Yoshio ; Mizutani, Tomoko ; Hiramoto, Toshiro
Author_Institution :
Low-power Electron. Assoc. & Project (LEAP), Tsukuba, Japan
fYear :
2013
fDate :
11-13 June 2013
Abstract :
We demonstrated record 0.37V minimum operation voltage (Vmin) of 2Mb Silicon-on-Thin-Buried-oxide (SOTB) 6T-SRAM. Thanks to the small variability of SOTB (AVT~1.3 mVμm) and adaptive back biasing (ABB), Vmin was lowered down to ~0.4 V regardless of temperature. Both fast access time and small standby leakage were achieved by ABB.
Keywords :
SRAM chips; elemental semiconductors; silicon; SRAM; Si; adaptive back biasing; silicon-on-thin-buried-oxide; voltage 0.37 V; voltage 0.4 V; Capacitance; Junctions; Logic gates; MOS devices; Random access memory; Transistors; Very large scale integration;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location :
Kyoto
ISSN :
0743-1562
Print_ISBN :
978-1-4673-5226-0
Type :
conf
Filename :
6576627
Link To Document :
https://search.ricest.ac.ir/dl/search/defaultta.aspx?DTC=49&DC=629128
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