DocumentCode
629133
Title
A 22nm 2.5MB slice on-die L3 cache for the next generation Xeon® processor
Author
Wei Chen ; Szu-Liang Chen ; Siufu Chiu ; Ganesan, Rajeshwari ; Lukka, Venkata ; Wei Wing Mar ; Rusu, Stefan
Author_Institution
Intel Corp., Santa Clara, CA, USA
fYear
2013
fDate
11-13 June 2013
Abstract
The 20-way set associative 2.5MB slice ported L3 cache for the multi-core Xeon® Processor uses 0.108 um2 cell in a 22nm tri-gate technology with 2.7TB maximum bandwidth. It is protected by double-error correction/triple-error detection ECC. The basic building block is designed to support floorplan style on each processor with large L3 cache. On die fuse storage enables high resolution repair coverage. Programmable transient voltage collapse writes assist (TVC-WA), wordline underdrive read assist (WLUD-RA) circuits (RWA) is used to achieve aggressive Vccmin goal. Per-die post silicon RWA fusing and per-die post silicon redundancy flow have significantly improved L3 cache Vccmin by more than 150mv.Shutoff per slice features has reduced SRAM leakage.
Keywords
SRAM chips; cache storage; error correction codes; error detection codes; integrated circuit layout; microprocessor chips; ECC; SRAM leakage; TVC-WA; WLUD-RA circuit; die fuse storage; double-error correction detection; floorplan style; memory size 2.5 MByte; multicore Xeon processor; next generation Xeon processor; per-die post silicon RWA fusing; per-die post silicon redundancy flow; programmable transient voltage collapse writes assist circuit; repair coverage; size 22 nm; slice on-die L3 cache; tri-gate technology; triple-error detection; wordline underdrive read assist circuit; Arrays; Fuses; Random access memory; Redundancy; Silicon; Switching circuits; Transistors;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location
Kyoto
ISSN
0743-1562
Print_ISBN
978-1-4673-5226-0
Type
conf
Filename
6576632
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