Title :
A novel bit alterable 3D NAND flash using junction-free p-channel device with band-to-band tunneling induced hot-electron programming
Author :
Hang-Ting Lue ; Kuo-Ping Chang ; Chih-Ping Chen ; Ten-Hao Yeh ; Tzu-Hsuan Hsu ; Pei-Ying Du ; Yen-Hao Shih ; Chih-Yuan Lu
Author_Institution :
Emerging Central Lab., Macronix Int. Co., Ltd., Hsinchu, Taiwan
Abstract :
We demonstrate a novel p-channel 3D stackable NAND Flash that uses completely new programming and erasing methods. The p-channel 3D NAND avoids the disadvantage of GIDL induced hole erase of floating body n-channel NAND, giving a highly efficient -FN hole erasing and negligible disturb on the SSL and GSL devices. The p-channel NAND structure enables a novel -FN erase selection method, providing a unique feature of bit alterable erase that facilitates small-unit random code overwrite without block erase. Furthermore, the band-to-band tunneling induced hot-electron programming method provides lower operation voltage and is good for peripheral CMOS scaling. The device concept is demonstrated on a 37.5nm half-pitch 3D vertical gate (VG) junction-free NAND architecture.
Keywords :
CMOS integrated circuits; NAND circuits; flash memories; programmable logic devices; three-dimensional integrated circuits; tunnelling; band-to-band tunneling induced hot-electron programming method; block erase; floating body n-channel NAND; half-pitch 3D vertical gate (VG) junction-free NAND architecture; highly efficient -FN hole erasing; novel -FN erase selection method; p-channel 3D stackable NAND Flash; peripheral CMOS scaling; small-unit random code overwrite; Arrays; CMOS integrated circuits; Flash memories; Junctions; Logic gates; Programming; Thin film transistors;
Conference_Titel :
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5226-0