Study of the interference and disturb mechanisms of split-page 3D vertical gate (VG) NAND flash and optimized programming algorithms for multi-level cell (MLC) storage

Author

Chih-Chang Hsieh ; Hang-Ting Lue ; Yung Chun Li ; Kuo-Ping Chang ; Hsing Chen Lu ; Hsiang-Pang Li ; Wei-Chen Chen ; Yi-Hsuan Hsiao ; Shuo-Nan Hung ; Ti-Wen Chen ; Yen-Hao Shih ; Chih-Yuan Lu

Author_Institution

Emerging Central Lab., Macronix Int. Co., Ltd., Hsinchu, Taiwan

fYear

2013

fDate

11-13 June 2013

Abstract

Multi-level cell (MLC) programming is of crucial importance to make a cost competitive NAND Flash product. In conventional 2D floating gate NAND Flash, the interference and disturb become very severe as technology scales, and many methods have been adopted to alleviate the interferences. In 3D NAND, the pitch is generally larger and the charge-trapping device naturally has smaller interference. However, disturb and interference now come from three dimensions and new understanding of device properties must be gained in order to achieve MLC operation.

Keywords

NAND circuits; flash memories; 2D floating gate NAND Flash; 3D NAND; MLC operation; MLC programming; MLC storage; VG NAND flash; charge-trapping device; cost competitive NAND flash product; device property; disturb mechanisms; interference; multilevel cell programming; multilevel cell storage; optimized programming algorithms; split-page 3D vertical gate NAND flash; technology scales; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2013 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Print_ISBN

978-1-4673-5226-0

Type

conf

Filename

6576639