Performance of GAA poly-Si nanosheet (2nm) channel of junctionless transistors with ideal subthreshold slope

Author

Hung-Bin Chen ; Yung-Chun Wu ; Chun-Yen Chang ; Ming-Hung Han ; Nan-Heng Lu ; Ya-Chi Cheng

Author_Institution

Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

11-13 June 2013

Abstract

A junctionless (JL) gate-all-around (GAA) nanosheet polycrystalline silicon (poly-Si) 2nm channel thin-film transistor (TFT) has been successfully demonstrated. The sub-threshold swing (SS) of 61 mV/decade has been the record reported to date in JL TFTs, and the I_on/I_off current ratio is 10⁸. The cumulative distribution in nanosheet 2-nm channel is small. JL-GAA TFTs show a low drain-induced barrier lowering (DIBL) value of 6 mV/V for L_G=60nm, excellent gate control and reduced sensitivity to temperature in terms of V_TH and SS. The JL-GAA TFTs of good device characteristics along with simple fabrication are highly promising for future (system-on-panel) SOP and system-on-chip (SOC) applications.

Keywords

elemental semiconductors; field effect transistors; nanoelectronics; nanostructured materials; polymers; silicon; statistical distributions; thin film transistors; DIBL value; GAA poly-Si nanosheet channel; I_on/I_off current ratio; JL gate-all-around nanosheet polycrystalline silicon; JL-GAA TFT; SS; Si; cumulative distribution; device characteristics; drain-induced barrier lowering value; gate control; junctionless transistor; sensitivity; size 2 nm; size 60 nm; subthreshold slope; subthreshold swing; thin-film transistor; Fabrication; Logic gates; Nanoscale devices; Plasma temperature; Temperature; Temperature sensors; Thin film transistors;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology (VLSIT), 2013 Symposium on

Conference_Location

Kyoto

ISSN

0743-1562

Print_ISBN

978-1-4673-5226-0

Type

conf

Filename

6576657