DocumentCode :
629178
Title :
Scaling challenges of packaging in the Era of Big Data
Author :
Orii, Y. ; Horibe, A. ; Toriyma, Kazushige ; Matsumoto, Kaname ; Noma, Haruo ; Kohara, S. ; Sueoka, Kazuhisa ; Mori, Hisamichi
Author_Institution :
IBM Res. - Tokyo., Kawasaki, Japan
fYear :
2013
fDate :
11-13 June 2013
Abstract :
The exascale computing is required in the Era of Big Data. In order to achieve this demand, new technology innovation must be required and packaging scaling including 3D-IC with TSV (Through Silicon Vias) is one of most promising technology. To increase the total bandwidth, the fine pitch die to die interconnection is necessary. Micro-bumping, thermally enhanced underfill and advanced interposer technologies are one of the key technologies. Material selection for reliable fine-pitch interconnection has become a critical challenge in 3D chip stacking. Underfill material between die to die is also very important to reduce the total packaging stress and to enhance the vertical thermal conductivity. Low CTE high density organic substrate is emerging technology for 2.5D structure.
Keywords :
chip scale packaging; fine-pitch technology; integrated circuit interconnections; three-dimensional integrated circuits; 3D chip stacking; 3D-IC; TSV; advanced interposer technologies; big data; exascale computing; fine pitch die to die interconnection; low CTE high density organic substrate; material selection; microbumping; packaging scaling; technology innovation; thermally enhanced underfill; through silicon vias; total packaging stress; underfill material; vertical thermal conductivity; Joints; Nickel; Silicon; Substrates; Thermal conductivity; Tin;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location :
Kyoto
ISSN :
0743-1562
Print_ISBN :
978-1-4673-5226-0
Type :
conf
Filename :
6576677
Link To Document :
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