Title :
An integrated air gap structure to achieve high-performance TSV interconnects for 28nm 3D-IC integration
Author :
Liao, E.B. ; Cheng, K.W. ; Chen, Y.H. ; Teng, H.A. ; Chen, Y.H. ; Tseng, Y.C. ; Tsai, W.C. ; Chen, J.H. ; Lin, T.C. ; Yang, K.F. ; Lin, Y.C. ; Chang, H.B. ; Wei, T.S. ; Chen, H.Y. ; Chen, Mayee F. ; Hsieh, C.C. ; Wu, T.J. ; Wu, Cathy H. ; Shih, D.Y. ; Chi
Author_Institution :
R&D, Taiwan Semicond. Manuf. Co., Ltd., Hsinchu, Taiwan
Abstract :
A novel air gap (AG) structure is integrated into TSV formation to achieve high performance interconnects for 3D stacking of 28nm CMOS devices. When benchmarked against conventional TSVs, the most prominent advantages of this novel TSV structure demonstrated reduced capacitance, minimized TSV-induced stress and, hence, reduced keep-out zone (KOZ) for CMOS devices. Our FEM simulation confirms that the inserted air gap alleviates the TSV proximity effect and safeguards the CMOS device performance. The structural integrity of this TSV structure is demonstrated by its robust electrical characteristics and compatibility with the subsequent BEOL metallization.
Keywords :
CMOS integrated circuits; finite element analysis; integrated circuit interconnections; three-dimensional integrated circuits; 3D stacking; 3D-IC integration; BEOL metallization; CMOS device; FEM simulation; TSV proximity effect; TSV-induced stress; capacitance; high-performance TSV interconnects; integrated air gap structure; robust electrical characteristic; size 28 nm; structural integrity; CMOS integrated circuits; Capacitance; MOSFET circuits; Metallization; Stress; Through-silicon vias; Very large scale integration; KOZ; TSV; air gap; parasitic capacitance;
Conference_Titel :
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5226-0
