DocumentCode
629185
Title
Demonstration of InGaAs/Ge dual channel CMOS inverters with high electron and hole mobility using staked 3D integration
Author
Irisawa, T. ; Oda, Masaomi ; Kamimuta, Y. ; Moriyama, Y. ; Ikeda, Ken-ichi ; Mieda, E. ; Jevasuwan, W. ; Maeda, T. ; Ichikawa, Osamu ; Osada, Takenori ; Hata, Masaharu ; Tezuka, Taro
Author_Institution
Collaborative Res. Team Green Nanoelectron. Center (GNC), AIST, Tsukuba, Japan
fYear
2013
fDate
11-13 June 2013
Abstract
We have successfully fabricated high mobility dual channel CMOS inverters composed of InGaAs nMOSFETs and Ge pMOSFET utilizing stacked 3D integration, for the first time. The inverter operation down to Vdd = 0.2 is demonstrated. InGaAs layers were bonded on Ge pMOSFETs and processed to form nMOSFETs. No degradation of Ge pMOSFETs during InGaAs nMOSFETs process was observed. Mobility enhancement of 2.6× and 3.0× for InGaAs nMOSFETs and Ge pMOSFETs, respectively, were realized after the stacking processes.
Keywords
CMOS logic circuits; gallium arsenide; logic gates; three-dimensional integrated circuits; dual channel CMOS inverters; high electron; hole mobility; nMOSFET; pMOSFET; staked 3D integration; CMOS integrated circuits; Fabrication; Indium gallium arsenide; Inverters; Logic gates; MOSFET; MOSFET circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology (VLSIT), 2013 Symposium on
Conference_Location
Kyoto
ISSN
0743-1562
Print_ISBN
978-1-4673-5226-0
Type
conf
Filename
6576684
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