Hardware implementation of truncated multiplier based on multiplexer using FPGA

The paper is about the implementation of PCT multiplier whose design is based on multiplexer using Field Programmable Gate Array (FPGA). Multiplier is such an important element from the point of power consumption and area occupied in the system. Multiplication using truncated scheme provides an efficient method for reducing the power and area as compared to that of full width multipliers. There are many schemes for truncation in multiplier among them an adaptive pseudo-carry compensation truncation (PCT) scheme gives result with low error. This scheme is suitable to array multiplier designed using multiplexer based technique. The comparative result between the two multipliers in this paper., PCT multiplier occupies just about 34% more area with approximately 38% less power consumption and with low error probability. The designed PCT multiplier is power efficient and faster than the compared one in terms of propagation delay. The future scope is it can be used for image compression by implementation on Field Programmable Gate Array (FPGA).