Design of control circuit for adaptive flash ADC

This paper presents a proposed design of Peak Detector and Sub-Flash architecture for adaptive ADC. The control circuits are developed for Adaptive Resolution for Flash ADC. Peak detector circuits will consist of peak detector for variable resolution and sub-flash architecture for reconfigurability. The voltages from the Bias block are used to provide a control voltage for Peak Detector circuits. The Transient analysis for peak detector circuits are tested for pulse and sinusoidal input voltage and the settling time is reported to be 5ns and 10ns. For reconfigurability the vin is compared with Bias Block voltages for achieving the resolution i.e, 4 bit, 5 bit, 6 bit respectively.