Low power and low area design for advanced encryption standard and fault detection scheme for secret communications

Advanced Encryption Standard has been built as the first choice for many cryptographic applications because of the high level of security. Data Security is primary concern for communication system. There are many methods to provide security data that is being communicated. However, security is assured irrespective of the hackers are from the noise. This paper presents a low power and low area design for the Advanced Encryption Standard based on an 8-bit data path. It has significant power-area-latency performance improvements over normal 128-bit data path AES. Such improvements are achieved by the use of resource sharing, simple compact memory architecture, Low Resource MixColumn Circuit, minimizing memory transfers and avoiding unnecessary switching activity. In addition to the performance requirements of the AES, it must be reliable against transient or permanent internal faults. The faults that accidently occur in the hardware implementations of the AES may cause erroneous output. At the end of the design, this paper presents parity-based fault detection scheme for high performance AES implementations.