VLSI implementation of Piecewise Approximated antilogarithmic converter

Applications such as signal and image processing require a dedicated hardware unit for logarithmic conversion due to the large delay involved in software techniques which make them unsuitable for real time applications. In this paper, Piecewise Approximation approach based on Linear Programming technique has been proposed for antilogarithmic converter design, which achieves minimum total relative approximation error due to optimized coefficients obtained. Multipliers have been avoided in the design by utilizing shifters and adders which reduces design complexity. Hardware efficiency and high speed operation are feasible using a small LUT to store the coefficient values. The area and power requirements have been analyzed for the VLSI implementation using Cadence Encounter RTL compiler.