A high speed power efficient pipeline ADC in 0.18μm CMOS

This paper describes a 12 bit pipeline ADC with conversion rate of 160 MS/s. A 2.5 bit non-flip-around MDAC structure is used in each stage which reduces total number of stages and total amount of sampling capacitance and consequentially power consumption of the ADC. Two-stage indirect compensated opamp with different phase margins in sampling and amplifying modes is embedded in the MDAC and to achieve required accuracy, dc-gain of the opamp is increased using positive feedback in the first stage of the opamp. Simulation results with Spice in 0.18 μm at a temperature of 75°C confirm that with a sampling rate of 160 Ms/s SNDR is 65.6 dB and power consumption is 103 mw where supply voltage is 1.8 V.