Title :
Power reduction methodology in 28nm SOC production design — What have changed?
Author_Institution :
Cadence Design Syst., Dallas, TX, USA
Abstract :
Device power characteristic changes significantly in 28nm CMOS technology. Consequently, some power reduction design methods that had been effective and successful in larger technology nodes become less effective or no longer useful in 28nm CMOS designs. This paper describes such changes in power reduction methods from production SOC design perspective.
Keywords :
CMOS integrated circuits; integrated circuit design; low-power electronics; system-on-chip; CMOS designs; device power characteristic; power reduction design methods; production SOC design perspective; size 28 nm; CMOS integrated circuits; CMOS technology; Logic gates; Optimization; Production; System-on-chip; Timing; 28nm SOC; design methodology; low power;
Conference_Titel :
Faible Tension Faible Consommation (FTFC), 2013 IEEE
Conference_Location :
Paris
Print_ISBN :
978-1-4673-6105-7
DOI :
10.1109/FTFC.2013.6577757
