Title :
High speed ultra low-voltage differential D Flip-Flop for low-voltage CMOS design
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we present a novel differential CMOS D Flip-Flop based on a high-current pass transistor. We use floating capacitors to obtain a current boost at specific events, i.e clock edges. The Flip-Flop presented may be used in any low voltage digital CMOS systems. The delay is reduced to approximately 12% compared to a conventional sense. amplifier differential Flip-Flop. The simulated data provided is obtained using Cadence and 90nm TSMC CMOS process.
Keywords :
CMOS logic circuits; flip-flops; high-speed integrated circuits; logic design; Cadence; TSMC CMOS process; clock edges; current boost; floating capacitors; high speed ultra low-voltage differential D flip-flop; high-current pass transistor; low voltage digital CMOS systems; low-voltage CMOS design; size 90 nm; CMOS integrated circuits; Clocks; Delays; Flip-flops; MOS devices; Threshold voltage; Transistors;
Conference_Titel :
Faible Tension Faible Consommation (FTFC), 2013 IEEE
Conference_Location :
Paris
Print_ISBN :
978-1-4673-6105-7
DOI :
10.1109/FTFC.2013.6577763
