Title :
Robust low-power CMOS precharge logic
Author :
Mirmotahari, O. ; Berg, Yngvar
Author_Institution :
Dept. of Inf., Univ. of Oslo, Oslo, Norway
Abstract :
In this paper we improve the Ultra Low-Voltage gate by including a keeper transistor at the floating-gate to make the gate more static. Thus, the refresh overhead is excluded, in addition the power consumption in evaluation period is significant lower. We also evaluate the gates behaviour for the effect of delayed input signal. All results are obtained by simulation in Cadence for a 90 nm process parameters.
Keywords :
CMOS logic circuits; MOSFET; circuit simulation; low-power electronics; Cadence simulation; input signal delay effect; keeper transistor; low-power CMOS precharge logic circuit; power consumption; size 90 nm; ultralow-voltage floating-gate; CMOS integrated circuits; Delays; Inverters; Logic gates; Low voltage; Power demand; Transistors; 90nm; Cadence; Domino logic; Floating-Gate; Low-Power; Precharge logic; Refresh; Static CMOS; Ultra Low-Voltage;
Conference_Titel :
Faible Tension Faible Consommation (FTFC), 2013 IEEE
Conference_Location :
Paris
Print_ISBN :
978-1-4673-6105-7
DOI :
10.1109/FTFC.2013.6577764
