Energy limits in A/D converters

Driven by ever-increasing application demands, the energy expended per A/D conversion has improved substantially over the last decade. This paper surveys the most recent trends and investigates practical energy limits of A/D converter architectures that are commonly employed in fine-line CMOS technology. We observe that today´s most efficient converters operate at about two orders of magnitude above the classical 8kT·SNR thermal limit. Furthermore, it is shown that a large fraction of today´s designs have approached ideal thermal limit lines, corresponding to a four-fold increase in energy per bit of resolution.