A 32nm, 0.9V Supply-noise sensitivity tracking PLL for improved clock data compensation featuring a deep trench capacitor based loop filter

An adaptive PLL implemented in a 0.9V 32nm process achieves optimal clock data compensation across a wide range of PVT and operating conditions. This is accomplished by an automated supply-noise sensitivity tracking loop which constantly monitors the BER of a tunable critical path circuit. The proposed PLL achieves a 14.5% to 15.6% improvement in processor Fmax over a conventional design for a 90mV supply noise and has a 92.1% smaller area by employing ultra-high density deep trench capacitors in the loop filter.