A 0.6V resistance-locked loop embedded digital low dropout regulator in 40nm CMOS with 77% power supply rejection improvement

Author

Chao-Chang Chiu ; Po-Hsien Huang ; Lin, Man ; Ke-Horng Chen ; Ying-Hsi Lin ; Tsung-Yen Tsai ; Chen-Chih Huang ; Chao-Cheng Lee

Author_Institution

Inst. of Electr. Control Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

2013

fDate

12-14 June 2013

Abstract

Conventional analog low dropout regulators suffer from serious degradations in its bandwidth, PSR, and regulation performance under sub-1V operation. The proposed digital LDO with the embedded resistance-locked loop (RLL) controller fabricated in 40nm CMOS process can still correctly regulate the output voltage to 0.4 V even when the input voltage scales down to 0.6V. Besides, maximum load current reaches 200mA and the switching noise suppression can be effectively improved by 77% compared to the state-of-the-art digital LDOs.

Keywords

CMOS digital integrated circuits; embedded systems; integrated circuit noise; microcontrollers; CMOS process; analog low dropout regulators; current 200 mA; digital low dropout regulator; embedded resistance-locked loop controller; power supply rejection improvement; size 40 nm; switching noise suppression; voltage 0.4 V; voltage 0.6 V; voltage 1 V; Arrays; MOSFET; Noise; Regulators; Switches; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578649