• DocumentCode
    629993
  • Title

    An 8.5 mW, 0.07 mm2 ADPLL in 28 nm CMOS with sub-ps resolution TDC and < 230 fs RMS jitter

  • Author

    Bo Shen ; Unruh, Greg ; Lugthart, Marcel ; Chang-Hyeon Lee ; Chambers, Mark

  • Author_Institution
    Broadcom Corp., Irvine, CA, USA
  • fYear
    2013
  • fDate
    12-14 June 2013
  • Abstract
    An All-Digital PLL (ADPLL) in 28 nm CMOS is designed to generate low noise clocks for high-speed ADCs. A high-resolution (<; 1 ps), short-span (6 ps) Time-to-Digital Converter (TDC) is implemented to improve the phase noise with little cost of power and area. This ADPLL has <; 230 fs RMS jitter at 50 MHz reference frequency, with 8.5 mW power from 1.8V supply and an area of 0.07 mm2.
  • Keywords
    CMOS integrated circuits; digital phase locked loops; jitter; phase noise; time-digital conversion; ADPLL; RMS jitter; TDC; all-digital PLL; frequency 50 MHz; high-speed ADC; low noise clocks; phase noise; power 8.5 mW; size 28 nm; time 6 ps; time-to-digital converter; voltage 1.8 V; CMOS integrated circuits; Clocks; Delays; Jitter; Phase locked loops; Phase noise; ADPLL; TDC; limit-cycle; quantization noise;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2013 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-5531-5
  • Type

    conf

  • Filename
    6578658
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=629993