DocumentCode
629994
Title
A 12GHz 210fs 6mW digital PLL with sub-sampling binary phase detector and voltage-time modulated DCO
Author
Ru, Zhiyu ; Geraedts, P. ; Klumperink, E. ; He, Xiangning ; Nauta, Bram
Author_Institution
Univ. of Twente, Enschede, Netherlands
fYear
2013
fDate
12-14 June 2013
Abstract
An integer-N digital PLL architecture is presented that simplifies the critical phase path using a sub-sampling binary (bang-bang) phase detector. Two power-efficient techniques are presented that can reduce DCO frequency tuning step by voltage-domain and time-domain (pulse-width) modulating the DCO LSB varactors. Measurement shows 210fs RMS jitter at 11.8GHz DCO frequency and 6mW power.
Keywords
digital phase locked loops; jitter; microwave oscillators; phase detectors; varactors; DCO LSB varactors; DCO frequency tuning; RMS jitter; critical phase path; digitally-controlled oscillator; frequency 12 GHz; integer-N digital PLL architecture; power 6 mW; power-efficient techniques; subsampling binary phase detector; time 210 fs; time-domain modulation; voltage-domain modulation; voltage-time modulated DCO; Capacitors; Detectors; Frequency modulation; Jitter; Phase locked loops; Phase noise;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578659
Link To Document