Title :
A 25GHz 100ns lock time digital LC PLL with an 8-phase output clock
Author :
Navid, Reza ; Hekmat, Mohammad ; Aryanfar, Farshid ; Wei, Jason ; Gadde, Vijay
Author_Institution :
Rambus Inc., Sunnyvale, CA, USA
Abstract :
A digital LC PLL in a 40nm CMOS technology achieves a 100ns lock time and a 16% tuning range while producing an 8-phase output clock with less than 2° phase error up to 25GHz. Fast lock is achieved by calibrating the phase of the feedback clock. The 8-phase output clock is generated using a loop of four digitally-controlled magnetically-coupled LC oscillators. The architecture is suitable for fast-wakeup links.
Keywords :
CMOS digital integrated circuits; clocks; digital phase locked loops; 8-phase output clock; CMOS technology; digital phase-locked loops; digitally-controlled magnetically-coupled LC oscillators; fast-wakeup links; feedback clock; frequency 25 GHz; lock time digital LC PLL; size 40 nm; time 100 ns; CMOS integrated circuits; CMOS technology; Clocks; Inductors; Jitter; Phase locked loops; Phase noise;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
