DocumentCode
629996
Title
A 28GHz hybrid PLL in 32nm SOI CMOS
Author
Ferriss, Mark ; Rylyakov, A. ; Ainspan, Herschel ; Tierno, Jose ; Friedman, Daniel
Author_Institution
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
fYear
2013
fDate
12-14 June 2013
Abstract
A hybrid PLL is introduced, which features a simple switched resistor analog proportional path filter in parallel with a highly digital integral path. The integral path control scheme for the LC-tank VCO includes a novel linearly scaled capacitor bank configuration. At 28 GHz the RMS jitter is 199fs (1MHz to 1GHz), phase noise is -110dBc/Hz at 10MHz offset. The 140×160μm2 32nm SOI CMOS PLL locks from 23.8 to 30.2 GHz, and draws 31mA from a 1V supply.
Keywords
CMOS integrated circuits; MMIC oscillators; field effect MMIC; jitter; phase locked loops; phase noise; silicon-on-insulator; switched filters; voltage-controlled oscillators; LC-tank VCO; SOI CMOS; current 31 mA; frequency 23.8 GHz to 30.2 GHz; hybrid PLL; integral path control scheme; linearly scaled capacitor bank configuration; phase locked loops; phase noise; silicon-on-insulator; size 32 nm; switched resistor analog proportional path filter; voltage 1 V; Phase locked loops; Phase noise; Switches; Tuning; Varactors; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578661
Link To Document