Title :
A 38% access time improvement in 40nm CMOS technology with Triple-Wire-Program-Cell scheme for high density MROM
Author :
Dozaka, Toshiaki ; Hojo, Toshiaki ; Yabe, Tatsuro ; Fukuda, Toshio ; Midorikawa, Tsuyoshi ; Kohara, Koji ; Hashimoto, Koji ; Wakiyama, Ichiro ; Uchino, Y. ; Otsuka, N.
Author_Institution :
Toshiba Corp., Kawasaki, Japan
Abstract :
This paper proposes a Triple-Wire-Program-Cell (TWPC) scheme and Triple-Line-Decoder (TLD) for high density MROM. TWPC consists of a cell transistor with triple wires (bit lines) and stores two-bit data in a cell. These designs have been implemented in 40nm test chips without cell array area overhead. The access time is improved by 38% with TWPC scheme in 40nm 1Mbit macro.
Keywords :
CMOS memory circuits; read-only storage; CMOS technology; TLD; TWPC scheme; cell array area; high density MROM; size 40 nm; test chips; triple-line-decoder; triple-wire-program-cell scheme; two-bit data; Arrays; CMOS integrated circuits; CMOS technology; Delays; Market research; Programming; Transistors;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
