DocumentCode
630013
Title
A Sub-1.0V 20nm 5Gb/s/pin post-LPDDR3 I/O interface with Low Voltage-Swing Terminated Logic and adaptive calibration scheme for mobile application
Author
Young-Chul Cho ; Yong-Cheol Bae ; Byoung-Mo Moon ; Yoon-Joo Eom ; Min-Su Ahn ; Won-Young Lee ; Cheong-Ryong Cho ; Min-Ho Park ; Young-Jin Jeon ; Jin-Oh Ahn ; Baek-Kyu Choi ; Dan-Kyu Kang ; Sang-Hyuk Yoon ; Yun-Seok Yang ; Kwang-Il Park ; Jung-Hwan Choi ;
Author_Institution
DRAM Design Team, Samsung Electron. Co., Hwaseong, South Korea
fYear
2013
fDate
12-14 June 2013
Abstract
A 5Gbp/s mobile memory I/O interface at sub-1.0V supply voltage with Low Voltage-Swing Terminated Logic (LVSTL) using a VSSQ (Ground) termination and an adaptive reference voltage calibration scheme is presented. Power efficiency is 2.4mW/Gbps/pin in 20nm mobile DRAM process, which is 44% lower value than that of LPDDR3.
Keywords
DRAM chips; calibration; logic circuits; LVSTL; VSSQ; adaptive reference voltage calibration scheme; bit rate 5 Gbit/s; efficiency 44 percent; low voltage-swing terminated logic; mobile DRAM process; mobile application; mobile memory I-O interface; post-LPDDR3 I-O interface; size 20 nm; voltage 1.0 V; Bandwidth; Calibration; Mobile communication; Receivers; Training; Transceivers; Transmitters;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578678
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