DocumentCode
630020
Title
A 401GFlops/W 16-cores signal reconstruction platform with a 4G entries/s matrix generation engine for compressed sensing and sparse representation
Author
Yi-Min Tsai ; Tien-Ju Yang ; Liang-Gee Chen
Author_Institution
DSP/IC Design Lab., Nat. Taiwan Univ., Taipei, Taiwan
fYear
2013
fDate
12-14 June 2013
Abstract
A versatile signal reconstruction platform designed in a 40nm CMOS process is presented. The chip supports high-dimensional sparse signal reconstruction for compressed sensing and sparse representation. A 4G entries/s (8Gbps) high-throughput sensing matrix generation engine is proposed. It r educes o ver 75% external bandwidth and 77% processing cycles. The chip achieves 401GFlops/W power efficiency with 16 multi-processing cores. The chip also yields over 1000× improvement of computing time compared to software implementations.
Keywords
compressed sensing; microprocessor chips; signal reconstruction; 4G entry-matrix generation engine; bit rate 8 Gbit/s; compressed sensing; high-dimensional sparse signal reconstruction; high-throughput sensing matrix generation engine; multiprocessing cores; sparse representation; versatile signal reconstruction platform; Compressed sensing; Dictionaries; Engines; Matrix decomposition; Sensors; Signal reconstruction; Sparse matrices;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578685
Link To Document