A 2.1 mW 11b 410 MS/s dynamic pipelined SAR ADC with background calibration in 28nm digital CMOS

Author

Verbruggen, Bob ; Iriguchi, Masao ; de la Guia Solaz, Manuel ; Glorieux, Guy ; Deguchi, Kenta ; Malki, Badr ; Craninckx, Jan

Author_Institution

imec, Leuven, Belgium

fYear

2013

fDate

12-14 June 2013

Abstract

A 410 MS/s 2x interleaved 11bit pipelined SAR ADC in 28nm digital CMOS is presented. Each ADC channel consists of a 6b coarse SAR, a dynamic residue amplifier and a 7b fine SAR and includes an on-chip calibration engine that detects and corrects comparator offsets and amplifier gain errors in the background. The ADC achieves a peak SNDR of 59.8 dB at 410 MS/s for an energy per conversion step of 6.5 fJ.

Keywords

CMOS digital integrated circuits; amplifiers; analogue-digital conversion; comparators (circuits); pipeline processing; amplifier gain errors; background calibration; comparator offsets; digital CMOS; dynamic pipelined SAR ADC; dynamic residue amplifier; interleaved pipelined SAR ADC channel; on-chip calibration engine; peak SNDR; power 2.1 mW; size 28 nm; storage capacity 11 bit; CMOS integrated circuits; Calibration; Clocks; Engines; Gain; Histograms; Redundancy; calibration; pipelined SAR;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits (VLSIC), 2013 Symposium on

Conference_Location

Kyoto

Print_ISBN

978-1-4673-5531-5

Type

conf

Filename

6578690

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=630025