Title :
A 6b 10GS/s TI-SAR ADC with embedded 2-tap FFE/1-tap DFE in 65nm CMOS
Author :
Tabasy, Ehsan Zhian ; Shafik, Ayman ; Keytaek Lee ; Hoyos, Sebastian ; Palermo, Samuel
Author_Institution :
Analog & Mixed-Signal Center, Texas A&M Univ., College Station, TX, USA
Abstract :
A 64-way time-interleaved successive approximation based ADC front-end efficiently incorporates a 2-tap embedded FFE and a 1-tap embedded DFE, while achieving 4.56-bits peak ENOB at a 10GS/s sampling rate. Fabricated in 1.1V 65nm CMOS, the ADC with embedded equalization achieves 0.48 pJ/conv.-step FOM, while consuming 79.1mW and occupying 0.33mm2 core ADC area.
Keywords :
CMOS integrated circuits; analogue-digital conversion; ADC front end; embedded DFE; embedded equalization; power 79.1 mW; size 65 nm; successive approximation register; time interleaved successive approximation; voltage 1.1 V; CMOS integrated circuits; Calibration; Capacitors; Clocks; Decision feedback equalizers; Receivers; Timing; ADC; ADC-based receiver; DFE; FFE; SAR; embedded equalization; time interleaving;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
