DocumentCode
630029
Title
A 5Gb/s 2.6mW/Gb/s reference-less half-rate PRPLL-based digital CDR
Author
Guanghua Shu ; Saxena, Shanky ; Woo-Seok Choi ; Talegaonkar, Mrunmay ; Inti, Rajesh ; Elshazly, Amr ; Young, B. ; Hanumolu, Pavan Kumar
Author_Institution
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
fYear
2013
fDate
12-14 June 2013
Abstract
A reference-less half-rate digital CDR implements proportional control in phase domain with a phase-rotating PLL (PRPLL) which decouples jitter transfer (JTRAN) bandwidth and jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on phase detector gain. Fabricated in a 90nm CMOS process, the prototype CDR achieves 2MHz JTRAN, 16MHz JTOL, and consumes 13.1mW from 1V supply at 5Gb/s with BER<;10-12.
Keywords
CMOS digital integrated circuits; clock and data recovery circuits; jitter; phase detectors; phase locked loops; proportional control; CMOS process; JTOL; JTRAN; PRPLL; bit rate 5 Gbit/s; frequency 16 MHz; frequency 2 MHz; jitter peaking; jitter tolerance; jitter transfer; phase detector gain; phase-rotating phase locked loops; power 13.1 mW; power 2.6 mW; proportional control; reference-less half-rate digital CDR; size 90 nm; voltage 1 V; Bandwidth; Clocks; Detectors; Frequency control; Frequency locked loops; Jitter; Phase measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location
Kyoto
Print_ISBN
978-1-4673-5531-5
Type
conf
Filename
6578694
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