Title :
A fast power-on 2.2Gb/s burst-mode digital CDR with programmable input jitter filtering
Author :
Woo-Seok Choi ; Anand, Tejasvi ; Guanghua Shu ; Hanumolu, Pavan Kumar
Author_Institution :
Sch. of EECS, Oregon State Univ., Corvallis, OR, USA
Abstract :
A digital burst-mode CDR employs feed-forward data edge injection and a digital feedback loop to achieve instantaneous phase locking, data-rate tracking, and input jitter filtering. Fabricated in a 90nm CMOS process, the prototype receiver achieves instantaneous locking on the very first data edge and consumes 6.1mW at 2.2Gb/s. By controlling the edge injection rate, the proposed architecture allows variable JTRAN bandwidth from 5MHz to 40MHz.
Keywords :
CMOS digital integrated circuits; clock and data recovery circuits; feedback; feedforward; radio receivers; CMOS process; JTRAN; bandwidth 5 MHz to 40 MHz; bit rate 2.2 Gbit/s; burst mode digital CDR; clock and data recovery circuits; digital feedback loop; feedforward data edge injection; jitter transfer; phase locking; power 6.1 mW; programmable input jitter filtering; prototype receiver; size 90 nm; Bandwidth; Detectors; Frequency locked loops; Frequency measurement; Image edge detection; Jitter; Receivers;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
