3D stackable vertical-gate BE-SONOS NAND flash with layer-aware program-and-read schemes and wave-propagation fail-bit-detection against cross-layer process variations

This work demonstrates a 3D vertical-gate (3DVG) NAND Flash with circuit-level techniques to overcome degradations in speed, yield, and reliability resulting from cross-layer process variations. The key enables include: (1) layer-aware program-verify-and-read (LA-PV&R), (2) layer-aware-bitline-precharge (LA-BP), and (3) a wave-propagation (WP) fail-bit detection (FBD) scheme. A fabricated 2-layer 3DVG NAND testchip confirms that proposed layer-aware schemes achieve different target cell-program-threshold-voltages (V_THP) in each layer and a 40% reduction in sensing-margin (SM) loss due to background-pattern-dependency (BPD), with less than 0.1% area penalty for a Gb-scale 3DVG NAND. The WP-FBD also achieves a 9+x increase in FBD speed.