Title :
A 75.1dB SNDR 840MS/s CT ΔΣ modulator with 30MHz bandwidth and 46.4fJ/conv FOM in 55nm CMOS
Author :
Chi-Lun Lo ; Chen-Yen Ho ; Hung-Chieh Tsai ; Yu-Hsin Lin
Author_Institution :
MediaTek Inc., Hsinchu, Taiwan
Abstract :
This paper presents a 30MHz bandwidth continuous-time (CT) ΔΣ modulator with direct resistor feed-forward and fast excess loop delay (ELD) compensation method to enhance the loop stability. Moreover, the proposed design incorporates analog DAC background calibration and offset calibration for fully dynamic latch comparator. The modulator achieves 77.1dB DR and 75.1dB SNDR in 30MHz bandwidth, while occupying 0.071mm2 in 55nm CMOS and achieving a FoM (Power/(2BW·2ENOB)) of 46.4fJ/conv.
Keywords :
CMOS integrated circuits; delta-sigma modulation; CMOS integrated circuit; bandwidth 30 MHz; continuous-time delta-sigma modulator; digital-analog background calibration; direct resistor feedforward; excess loop delay compensation method; fully dynamic latch comparator; loop stability; offset calibration; size 55 nm; Active filters; Bandwidth; CMOS integrated circuits; Calibration; Latches; Modulation; Resistors;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
