Title :
A 4.1mW, 12-bit ENOB, 5MHz BW, VCO-based ADC with on-chip deterministic digital background calibration in 90nm CMOS
Author :
Sachin Rao ; Reddy, Karthikeyan ; Young, B. ; Hanumolu, Pavan Kumar
Author_Institution :
Sch. of EECS, Oregon State Univ. Corvallis, Corvallis, OR, USA
Abstract :
A deterministic digital background calibration technique to correct non-linearity in VCO-based ADCs is presented. Implemented in 90nm CMOS process, on-chip calibration improves SFDR of the prototype ADC from 46dB to more than 83dB. The ADC consumes 4.1mW power and achieves 73.9dB SNDR in 5MHz signal bandwidth.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; voltage-controlled oscillators; CMOS process; ENOB; SFDR; VCO-based ADC; bandwidth 5 MHz; noise figure 73.9 dB; nonlinearity; on-chip calibration; on-chip deterministic digital background calibration; power 4.1 mW; size 90 nm; Bandwidth; Calibration; Clocks; Signal to noise ratio; System-on-chip; Table lookup; Voltage-controlled oscillators;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
