• DocumentCode
    630062
  • Title

    Two-channel receiver back-end using statistically calibrated HRM with >70dB 3rd and 5th harmonic rejection for carrier aggregation in 32nm CMOS

  • Author

    Alpman, Erkan ; Verhelst, Marian ; Lakdawala, Hasnain

  • Author_Institution
    Intel Corp., Hillsboro, OR, USA
  • fYear
    2013
  • fDate
    12-14 June 2013
  • Abstract
    A wideband receiver back-end supporting dual band reception for carrier aggregation has been implemented in 32nm CMOS. The proposed architecture relies on tunable phase generation circuitries, feeding parallel paths consisting of a harmonic rejection mixer and a ΔΣ-ADC. 3rd and 5th order harmonic distortion is suppressed through statistical calibration, exploiting the inherent circuit variability, achieving HR3 and HR5 jointly exceeding 70dB when tested across multiple dies, while dissipating 16mW per back-end channel and covering a mixing range of 240MHz.
  • Keywords
    CMOS integrated circuits; analogue-digital conversion; mixers (circuits); radio receivers; statistical analysis; ΔΣ-ADC; CMOS; carrier aggregation; dual band reception; harmonic rejection mixer; statistically calibrated HRM; two-channel receiver; wideband receiver; Clocks; Harmonic analysis; Mixers; Power harmonic filters; Radio frequency; Receivers; Resistors; Carrier Aggregation and Statistical Calibration; Harmonic Rejection;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits (VLSIC), 2013 Symposium on
  • Conference_Location
    Kyoto
  • Print_ISBN
    978-1-4673-5531-5
  • Type

    conf

  • Filename
    6578727
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=630062