Title :
1Mb 0.41 µm2 2T-2R cell nonvolatile TCAM with two-bit encoding and clocked self-referenced sensing
Author :
Jing Li ; Montoye, R. ; Ishii, M. ; Stawiasz, Kevin ; Nishida, Tsutomu ; Maloney, Kim ; Ditlow, Gary ; Lewis, Simon John Geoffrey ; Maffitt, T. ; Jordan, Ramiro ; Chang, Ly-Yu ; Peilin Song
Author_Institution :
IBM T. J. Watson Res. Center, Yorktown Heights, NY, USA
Abstract :
This work demonstrates the first fabricated nonvolatile TCAM using 2-transistor/2-resistive-storage (2T-2R) cells to achieve >10x smaller cell size than SRAM-based TCAMs at the same technology node. The test chip was designed and fabricated in IBM 90nm CMOS technology and mushroom phase-change memory (PCM) process. To ensure reliable search operation with such compact cells, two enabling techniques were developed and implemented in hardware: 1) two-bit encoding, and 2) a clocked self-referenced sensing scheme (CSRSS). The 1Mb chip demonstrates reliable low voltage search operation (VDDmin~750mV) and a match delay of 1.9 ns under nominal operating conditions.
Keywords :
CMOS memory circuits; SRAM chips; clocks; content-addressable storage; integrated circuit design; integrated circuit reliability; low-power electronics; phase change memories; search problems; 2-transistor-2-resistive-storage cells; 2T-2R cells; CSRSS; IBM CMOS technology; PCM process; SRAM-based TCAM; bit rate 1 Mbit/s; cell nonvolatile TCAM; cell size; clocked self-referenced sensing scheme; compact cells; fabricated nonvolatile TCAM; low voltage search operation; match delay; mushroom phase-change memory process; reliable search operation; size 90 nm; technology node; test chip design; two-bit encoding; Arrays; Clocks; Encoding; Microprocessors; Phase change materials; Sensors;
Conference_Titel :
VLSI Circuits (VLSIC), 2013 Symposium on
Conference_Location :
Kyoto
Print_ISBN :
978-1-4673-5531-5
