Rump sessions

A crucial technology for almost every electronic system is the design of interface protocols and circuits for communication between CPU/controller and memory, especially DRAM. Recently, new applications such as mobile intelligent devices, cloud computing servers, multimedia consumer players, and others are emerging. These have driven various strategies for physical placement and connection of IC components. The conventional way of placing CPU and DRAM on a PCB in a twodimensional (2D) layout has now expanded to 2.5D, and the innovative use of 3D stacking to connect CPUs and DRAMs via WB (Wire Bonding) or TSV (Through Silicon Via). These 2D, 2.5D, and 3D designs have delivered major achievements in reducing power, shrinking form factors, enhancing speed, while in many cases controlling costs. As a result, interface technologies have drastically diverged instead of simply having one standard as successor to another. Thus, there are new designs such as: (1) DDRX: DDR3 to DDR4, and to DDR5, (2) LPDDRX: LPDDR2, LPDDR3 to LPDDR4, (3) Wide IO for TSV Dies, (4) Various interfaces proposed by Rambus, Mosys, etc. (5) Various SerDes Interfaces, (6) HMC (Hybrid Memory Cube), (7) RF Signal Transmission, and (8) Inductor or Capacitor Coupling designs, etc. Which is the best interface technology? Is there a single, overall winner? Will there be different winners for different 2D, 2.5D, or 3D IC designs, respectively? Will there be a divergence of low-power vs. high-performance (mobile vs. server) memory? The purpose of this panel is not to select the final champion among these emerging designs but to invite the world´s top designers and technologists to present and to debate on the pros and cons of these interface designs. Through this panel, we hope to stimulate discussions and empower the audience to make their own individual design choices in an optimal fashion.